A semiconductor device having a multilayer contact system typically includes a layer of a refractory metal silicide directly deposited on the surface of a monosilicon or polysilicon layer, a barrier layer of a refractory metal formed on the silicide layer, and a major or wiring electrode layer of, typically, aluminum. The metal silicide layer on the monosilicon or polysilicon layer is formed by depositing a high melting-point metal, viz., refractory metal such as platinum on the surface of the monosilicon or polysilicon layer and heating the metal to cause it to react with the monosilicon or polysilicon for forming the layer of the metal silicide on the monosilicon or polysilicon layer. The metal silicide has an electric resistance lower by tenths of a factor than that of polysilicon and is thus used to provide a low interconnection resistance without creating a p-n junction between the silicide layer and the underlying active region of the monosilicon or polysilicon layer. On the other hand, the barrier layer covering this silicide layer is used to prevent the topmost wiring electrode layer of aluminum from reacting with the metal silicide of the layer underlying the barrier layer. Silicon dissolves into aluminum during any subsequent high-temperature steps of the device fabrication process because of the relatively high solid solubility of silicon into aluminum at temperatures ordinarily used to form the aluminum layer on the titanium-tungsten layer. Thus, aluminum may propagate into the silicon substrate and thereby form pits or spikes of aluminum in the substrate. The aluminum spikes will penetrate through the p-n junction in the silicon substrate and will accordingly destroy the p-n junction. The barrier layer of the titanium-tungsten alloy is intended to prevent the device from being caused to fail by the destruction of the p-n junction due to formation of the aluminum spikes.
A well known example of a semiconductor device having a multilayer contact system uses platinum silicide (PtSi) as the refractory metal silicide layer and a titanium-tungsten alloy (Ti-W) as the barrier layer underlying the topmost aluminum layer. FIG. 1 of the drawings schematically shows the complete structure of a semiconductor device having such a three-level Al/Ti-W/PtSi contact system.
The prior-art semiconductor device illustrated in FIG. 1 includes a substrate 10 including a body portion 11 of p.sup.+ -type silicon which has a selected portion heavily doped with an n-type dopant such as arsenic or antimony to form a buried n.sup.+ -type diffusion region 12. On the resultant body portion 11 of the substrate 10 is epitaxially grown an n-type layer 14 which in part covers the n.sup.+ -type diffusion region 12. The substrate 10 thus includes the p-type silicon body portion 11, buried n.sup.+ -type diffusion region 12 and n-type epitaxial layer 14. The n-type epitaxial layer 14 is selectively oxidized with use of a mask of, for example, silicon nitride to form an isolation oxide layer 16 which is partially embedded in the silicon substrate 10. Into one selected portion of the island of the n-type epitaxial layer 14 which is thus isolated by the isolation oxide layer 16 is doped an n-type dopant such as arsenic or phosphorus typically by ion implantation techniques to form an n.sup.+ -type collector contact region 18 homogeneous with the buried n.sup.+ -type diffusion region 12. Into another selected portion of the island of the epitaxial layer 14 is heavily doped a p-type dopant such as boron to form a p-type base region 20 also typically by ion implantation techniques. A p-type dopant such as boron may be further introduced into a selected portion of this p-type base region 20 to form a heavily doped graft base area 20a having a reduced resistivity. On the entire surface of the resultant structure is formed a relatively thin first protective layer 22 of silicon oxide, which is then patterned and etched to form openings 22a, 22b and 22c. The opening 22a is located over the n.sup.+ -type collector contact region 18 and the opening 22c is located over the graft base area 20a of the p-type base region 20. The opening 22b is located over another area of the base region 20 as shown.
Polysilicon is then conformally deposited over the entire surface of the resultant structure to form a polysilicon layer in part on the surface of the first protective oxide layer 22 and in part on the silicon substrate 10 through the openings 22a, 22b and 22c in the oxide layer 22. The polysilicon layer is then patterned and etched away to leave regions 24a, 24b and 24c each in part contacting the silicon substrate 10 through each of the openings 22a, 22b and 22c, respectively, in the oxide layer 22 and in part overlying edge portions of the oxide layer 22 along each opening. In this instance, each of the regions 24a, 24b and 24c thus left of the polysilicon layer may have overlaps of about 1 micron with the edge portions of the oxide layer 22 along each of the openings 22a, 22b and 22c in the layer 22. The polysilicon regions 24a and 24b are then doped with an n-type dopant such as arsenic by ion implantation techniques, while the polysilicon region 24c is doped with a p-type dopant such as boron through the opening 22c in the oxide layer 22 also by ion implantation techniques. The entire structure is then heated at, for example, 950.degree. C. to anneal the polysilicon regions 24a, 24b and 24c. This annealing step is used not only to activate the atoms of the dopants implanted into the polysilicon regions 24a, 24b and 24c but to cause the n-type dopant in the polysilicon region 24b to partially diffuse into the p-type base region 20 to form an n-type emitter region 26 within the base region 20. The annealing step further lends itself to providing improved ohmic contact between the collector contact region 18 and the associated polysilicon region 24a, between the emitter region 26 and the associated polysilicon region 24b, and between the graft base area 20a of the base region 20 and the associated polysilicon region 24c. The n.sup.+ -type collector contact region 18, p-type base region 20 and n-type emitter region 26 as formed in the silicon substrate constitute in combination a semiconductor device in the form of a bipolar transistor.
A second protective layer 28 of silicon oxide is then conformally deposited on the entire surface of the resultant structure and is patterned and etched to form contact openings 28a, 28b and 28c over the doped polysilicon regions 24a, 24b and 24c, respectively. Through these contact openings 28a, 28b and 28c in the second protective oxide layer 28 is formed a multilayer contact system including a layer of platinum silicide as the refractory metal silicide, a barrier layer of titanium-tungsten alloy as the refractory metal, and a topmost wiring electrode layer of aluminum. A layer of platinum is thus deposited on the entire upper surfaces of the doped polysilicon regions 24a, 24b and 24c and the second protective oxide layer 28, whereupon heat treatment is used at 500.degree. C. to form platinum silicide layer regions 30a, 30b and 30c on the exposed upper surfaces of the doped polysilicon regions 24a, 24b and 24c, respectively, within the openings 25a, 25b and 25c, respectively, in the second protective oxide layer 28. The platinum layer remaining on the protective oxide layer 28 is removed before the barrier and wiring electrode layers are to be formed. After the barrier and wiring electrode layers are formed conformally on the surface of the resultant structure, the layers are patterned and etched to leave titanium-tungsten barrier layer regions 32a, 32b and 32c on the platinum silicide layer regions 30a, 30b and 30c, respectively, and wiring electrode layer regions 34a, 34b and 34c of aluminum on the titanium-tungsten barrier layer regions 32a, 32b and 32c, respectively.
In the prior-art semiconductor device having the multilayer contact systems thus arranged, the electrode stack 30c/32c/34c for the p-type base region 20 of the device remains in a stable state during every subsequent step of the device fabrication and packaging process and further when the device completed is in use. A problem is however encountered by the electrode stacks 30a/32a/34a and 30b/32b/34b for the n-type collector and emitter regions 18 and 26, respectively. The platinum silicide layer regions 30a and 30b of the electrode stacks for the collector and emitter regions 18 and 26 tend to be deficient in thickness and chemical homogeneousness of material and, for this reason, tend to cause contact failures during subsequent process steps or during use of the device. The reasons for this will be hereinafter explained with reference to FIGS. 2A to 2C as well as FIG. 1 of the drawings. In FIGS. 2A to 2C are shown, for simplicity of illustration, only those portions of the device described with reference to FIG. 1 which are associated with the electrode stack for the emitter region 26 of the device.
Referring to FIG. 2A, the silicon substrate 10 has the n-type layer 14 which has been epitaxially grown on the buried n.sup.+ -type diffusion region 12 (FIG. 1) of the substrate 10. In this n-type epitaxial layer 14 is locally formed the p-type base region 20 which is covered with the first protective layer 22 of silicon oxide formed with the opening 22b allowing the surface of the silicon substrate 10 to partly expose therethrough. Polysilcon is then deposited over the entire surface of the resultant structure to form a conformal polysilicon layer in part on the surface of the first protective oxide layer 22 and in part on the silicon substrate 10 through the opening 22b in the oxide layer 22. The polysilicon layer is then selectively etched away to leave regions including the region 24b in part contacting the silicon substrate 10 through the opening 22b in the oxide layer 22 and in part overlying edge portions of the oxide layer 22 along the opening 22b. As previously noted, the region 24b thus left of the plysilicon layer has overlaps of about 1 micron with the edge portions of the oxide layer 22 along the opening 22b in the layer 22. The polysilicon region 24b is then doped with an n-type dopant such as arsenic through the opening 22b in the oxide layer 22 by ion implantation techniques with a dosage of 1.times.10.sup.16 atoms/cm.sup.2. The entire structure is then heated at, for example, 950.degree. C. for 15 minutes to anneal the polysilicon region 24b, with the result that the n-type dopant in the polysilicon region 24b having a dopant concentration of 1.times.10.sup.19 atoms/cm.sup.3 or more is caused to partially diffuse into the p-type base region 20 to form the shallow n-type emitter region 26 within the base region 20. As previously noted, improved ohmic contact is provided between the emitter region 26 and the associated polysilicon region 24b as a result of this annealing step. The second protective layer 28 of silicon oxide is then conformally deposited on the entire surface of the resultant structure and is patterned and etched to form contact openings including the contact opening 28b allowing the surface of the doped polysilicon region 24b on the emitter region 26 to partly expose. Platinum is deposited by, for example, sputtering onto the entire surface of the structure to form a platinum layer 30 to a thickness of, for example, about 300 .ANG..
Heat treatment is then used to cause the platinum layer 30 to react with the polysilicon of the underlying polysilicon region 24b to form regions of platinum silicide which include the platinum silicide layer region 30b on the polysilicon region 24b as shown in FIG. 2B. In this instance, those portions of the platinum layer which overlie the second protective oxide layer 28 are not converted into silicide. The unreacted platinum layer on the second protective oxide layer 28 is removed by etching the layer. The platinum silicide layer region 30b thus formed is extremely thin and is lacking in uniformity of chemical composition and, for this reason, tends to cause contact failures during subsequent process steps or during use of the device as previously noted. Titanium-tungsten alloy is then deposited using sputtering techniques on the entire surface of the resultant structure to form a titanium-tungsten layer to a thickness of, for example, about 1000 .ANG.. Thereupon, aluminum is deposited, also by sputtering, on the surface of the titanium-tungsten layer to form an aluminum layer to a thickness of, for example, about 1 micron on the titanium-tungsten layer. These titanium-tungsten and aluminum layers are patterned and etched to leave titanium-tungsten barrier regions including the layer region 32b on the platinum silicide layer region 30b and wiring electrode regions including the layer region 34b of aluminum on the titanium-tungsten barrier layer region 32b as shown in FIG. 2B.
The platinum silicide layer region 30b forming part of the contact system for the emitter region 26 is extremely thin and is lacking in uniformity of chemical composition as above noted. During the subsequent high-temperature steps of the fabrication and packaging process or during uses of the device completed, reaction proceeds between the titanium-tungsten alloy of the barrier layer and the polysilicon in the doped polysilicon region 24b through a locally thinned or degraded portion of the platinum silicide layer region 30b and forms a new silicide such as tungsten silicide. The titanium-tungsten barrier layer per se serves as an excellent barrier to the aluminum layer but, once the tungsten silicide is formed through the platinum silicide layer, aluminum atoms in the overlying wiring electrode layer region 34b are allowed to diffuse through the tungsten silicide region and are enabled to react vitally with the polysilicon in the polysilicon region 24b. The reaction of aluminum atoms with the polysilicon may propagate through the emitter region 26 far into the base region 20 of the substrate 10. Penetration of such reaction across the p-n junction interface between the base and emitter regions 20 and 26 causes an aluminum spike as indicated at 36 in FIG. 2C. Formation of such an aluminum spike is serious especially for the emitter region 26 forming a shallow p-n junction with the base region 20 and will invite a complete failure of the device during the subsequent process steps or during use of the device as previously noted. This problem is encountered not only by semiconductor devices using Al/Ti-W/PtSi contact systems but also by those using other types of multilayer contact systems including a layer of a metal silicide and a layer of aluminum.
It is, accordingly, an important object of the present invention to provide an improved semiconductor device featuring an electrical multilayer contact system which remains in a stable state during the various steps, especially the high-temperature steps, of the device fabrication and packaging process subsequent to formation of the contact system and further throughout the use of the device fabricated.
It is another important object of the present invention to provide a process of fabricating such an improved semiconductor device.